A scan test of a large scaled integration semiconductor device (LSI) is performed using a combination of sequential circuits including a flip-flop (abbreviated to FF herein after) and a latch. It is not recommended to process a number of memory cells contained in the memory like the FFs and latches. This is because the number of FFs and latches becomes too much for a scan.
The memory itself can be diagnosed by BIST (Built in Self Test) and performance test. When performing a scan test, the memory can be treated as a black box that outputs input data as is, or a constant value. This is shown in FIGS. 7A and 7B. FIG. 7A illustrates the normal operation, while FIG. 7B illustrates a scan. In FIG. 8 an exemplary circuit is shown, which passes through the input data during the test of memory macro-cells. In the circuit shown in FIG. 8, mode signal TEN in high level (logic value 1) indicates a test mode, and TEN in low level (logic value 0) indicates the normal operation. A multiplexer is provided at the output of the output latch of memory to transfer the output signal from the output latch during the normal operation and to select the memory input data during the test mode operation. In this configuration the stored value of the latch is output as output data during the normal operation (FIG. 7A) while the memory input data is passed through during the test mode operation (FIG. 7B).
In a circuit shown in FIG. 8, the delay of the main path increases due to the multiplexer MUX added on the main path of the output latch. As a result the read out time of the memory cells is slowed down in the normal operation, causing the problem of decreasing the operation frequency of the final product. Along with the much larger scale integration, such additional circuits as BIST for LSI diagnosis are imperative. However, for a high-speed LSI, the delay of logic elements, which should fall within the operating cycle of the LSI, does not have enough margin with respect to the operating cycle of the LSI. In this situation the addition of extra circuits such as diagnosis circuit, which have no effect on the primary function of the LSI, increases the logic delay, resulting in a slower speed LSI.